The present invention relates to a bipolar transistor for a high frequency power amplifier that has a high gain with a small chip size and more particularly to a grounded emitter heterojunction bipolar transistor using a compound semiconductor.
With wide spread of portable radio terminals, performance of a high frequency power amplifier has been improved rapidly as well as decrease in cost. To increase the portability, it is necessary to reduce the number of batteries and supply voltage that has been strongly required recently. For that purpose, an HBT (heterojunction bipolar transistor) has been widely used which incorporate a GaAs series epitaxial wafer capable of highly efficient amplification even if the supply voltage becomes low. Such an epitaxial wafer is extremely expensive compared with the conventional Si substrate and GaAs substrate, so that it is an important problem to realize a power amplifier having a small chip area.
To portable terminals newly appeared recently, higher frequency bands have been allocated gradually. For example, in an analog portable telephone, a frequency of about 1 GHz is conventionally allocated, while in a recent digital portable telephone, the frequency is increased to about 2 GHz and furthermore, use of up to 5 GHz can be considered. When the frequency increases in this way, some improvements are device is necessary also for a method for mounting the power amplification transistor. Particularly, the inductance generated by a bonding wire connected to a ground electrode has serious problems.
Namely, since a high power transistor has a large element size, the input impedance decreases. Therefore, unless the ground inductance is reduced according to the element size, the portion of input signals applied to the transistor reduces and the power gain greatly decreases. Since the input impedance of the transistor is generally capacitive, the problem of the ground inductance is serious when the frequency is high. When the emitter is connected to the ground by wire bonding, it is necessary to increase the number of wires to make the ground inductance lower according to the element size. Therefore, although it is necessary to increase the number of bonding pads for grounding according to the element size, the chip area increases extremely since the bonding pad area is large, and thus the cost is increased inevitably.
FIG. 1 is a plane layout of a pattern showing an example of a conventional HBT. In this figure, a number of 32 transistor elements are formed at the central part of a semiconductor chip (1). However only emitter electrodes (2) of these elements are shown in FIG. 1. In the upper and lower peripherals of the semiconductor chip (1), a number of 12 bonding pads (3) are arranged. Although omitted in the drawing, the emitter electrodes (2) of 32 transistor elements are grouped properly and connected to each of the 12 bonding pads (3) by wire patterns formed in the semiconductor chip (1). Each bonding pad (3) is connected and grounded to a ground conductor provided outside the semiconductor chip (1) by a wire.
In such a conventional HBT, although 12 bonding wires are used to lower the emitter inductance, the ground inductance lowers only to 0.1 nH and the power gain is degraded greatly such as 9 dB. To install many bonding pads 3, it is necessary to make the chip area larger so that the area required to obtain an output of 30 dBm is 1.2.times.1.0 mm.sup.2.
Furthermore, even if a plurality of bonding wires are used, the inductance lowers only slowly rather than inversely proportional to the number of wires due to the mutual inductance between the wires and, thus, there is a limitation to the method for mounting the chip by conventional wire bonding.
Therefore, the method for boring a viahole in a GaAs substrate has been used as a method in place of bonding. The method, in a transistor formed on a semi-insulating GaAs substrate, bores a hole in the GaAs substrate under an emitter electrode pad by etching and connects the ground conductor provided on the back of the GaAs substrate and the emitter electrode by a plated wire. When the plated wire is used for connection, the inductance is small such as 1/10 or less of that by wire bonding. The ground inductance thus can be lowered sufficiently without increasing the number of emitter electrode pads with the high gain being maintained. Generally, however, to bore a viahole in a substrate, such a complicated process is required that the substrate is thinned to about 50 .mu.m and the processing is performed from the back of the substrate that is still an unskilled mass production art. Therefore, it cannot sufficiently comply with the demand for reduction in cost.
Another method for using a flip chip is available. With this method, a projection such as a gold bump is provided on an emitter electrode pad installed on the surface of a substrate. Then the substrate is turned upside down and connected to the ground surface. Therefore, the inductance of the emitter is extremely small and a high gain can be ensured. However, it is necessary to connect the electrodes other than the emitter with a bump, so that an advanced art and a special device are required for chip alignment. The method, thus, cannot sufficiently comply with the demand for reduction in cost.
As another conventional art available to the resolution of above problems, an art achieving satisfactory results in an Si-MOS field effect transistor will be described by referring to FIG. 2. In high-frequency power MOSFET for a portable terminal, n-channel MOSFET is produced using a p-type epitaxial layer (28) of low density on a p-type substrate (21) of high density. In this case, a p-type area (22) of high density is formed by diffusion until it reaches the p-type substrate from the surface. When the p-type area (22) is connected to a source electrode (23), the source electrode is connected to a ground electrode (29) on the back of the substrate with low impedance via the p-type substrate (21) of high density. With this method, no special process is required and hence a power transistor suited to the high-frequency operation can be formed at low cost.
However, in the diffusion process of forming the area (22) for connecting the source area to the p-type substrate, a problem arises that upper diffusion of boron which is acceptor impurities included in the substrate (21) progresses at the same time and control of the thickness of the low density layer (28) is difficult. In this structure, the ground capacity connected to the base wires and collector wires is large since the substrate is conductive. When the ground capacity is designed to be included in the impedance matching circuit, the performance such as power gain will not be degraded. However, as mentioned above, it is difficult to control the thickness of the low-density area (28). Consequently, a problem arises that the ground capacity connected to the base wires and collector wires varies greatly and the design precision may be lost.
Further, for GHz band power amplification, an npn bipolar transistor having an buried collector structure has been used. FIG. 3 schematically shows a cross sectional structure of a bipolar transistor having an buried collector layer generally used. Such a transistor is produced by diffusing n-type impurities of high density selectively on a p-type Si substrate (30) of low density, forming an buried collector area (31), growing an epitaxial layer (32) of low density, and then forming a p-type base area (37) and an n-type emitter area (38) by selective diffusion. In this case, the diffusion process for the buried collector layer and the epitaxial growth process of the low-density layer (32) require a high-temperature process. Although it is tried produce a high-frequency bipolar transistor having an buried collector layer stacked on a conductive substrate an epitaxial layer of low density further stacked on the buried collector layer, it is impossible to maintain a desired carrier profile due to existence of this high-temperature process.
Due to the obstacle relating to the manufacturing method, the method for lowering the ground inductance using a conductive substrate in a bipolar transistor cannot be used for a bipolar transistor used for high-frequency power amplification.